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ISL5239
Data Sheet July 2002 FN8039.1
Pre-Distortion Linearizer
The ISL5239 Pre-Distortion Linearizer (PDL) is a full featured component for Power Amplifier (PA) linearization to improve PA power efficiency and reduce PA cost. The Radio Frequency (RF) PA is one of the most expensive and power-consuming devices in any wireless communication system. The ideal RF PA would have an entirely linear relationship between input and output, expressed as a simple gain which applies at all power levels. Unfortunately, realizable RF amplifiers are not completely linear and the use of predistortion techniques allows the substitution of lower cost/power PA's for higher cost/power PA's. The ISL5239 pre-distortion linearizer enables the linearization of less expensive PA's to provide more efficient operation closer to saturation. This provides the benefit of improved linearity and efficiency, while reducing PA cost and operational expense. The ISL5239 features a 125MHz pre-distortion bandwidth capable of full 5th order intermodulation correction for signal bandwidths up to 20MHz. This bandwidth is particularly well suited for 3G cellular deployments of UMTS and CDMA2000. The device also corrects for PA memory effects that limit predistortion performance including self heating. The ISL5239 combines an input formatter and interpolator, predistortion linearizer, an IF converter, correction filter, gain/phase/offset adjustment, output formatter, and input and feedback capture memories into a single chip controlled by a 16bit linearizer interface. The ISL5239 supports log of power, linear magnitude, and linear power based pre-distortion, utilizing two Look-Up Table (LUT) based algorithms for the pre-distortion correction. The device provides programmable scaling and offset correction, and provides for phase imbalance adjustment.
Features
* Output Sample Rates Up to 125MSPS * Full 20MHz Signal Bandwidth * Dynamic Memory Effects Compensation * Input and Feedback Capture Memories * LUT-based Digital Pre-distortion * Two 18-bit Output Busses with Programmable Bit-Width * 16-Bit Parallel Processor Interface * Input Interpolator x2, x4, x8 * Programmable Frequency Response Correction * Low Power Architecture * Threshold Comparator for Internal Triggering * Quadrature or Digital IF Architecture * Lowest-Cost Full-Featured Part Available
Applications
* Base Station Power Amplifier Linearization * Operates with ISL5217 in Software Radio Solutions * Compatible with the ISL5961 or ISL5929 D/A Converters
Ordering Information
PART NUMBER ISL5239KI ISL5239EVAL1 TEMP RANGE (oC) -40 to 85 25 PACKAGE 196 Ld BGA Evaluation Kit PKG. DWG. # V196.15x15
Block Diagram
SERCLK SERSYNC SEROUT SERIN INPUT FORMATTER AND INTERPOLATOR X1, X2, X4, X8 PRE-DISTORTER WITH TWO 1K x 60 LUTs IF CONVERTER REAL 1X REAL 2X COMPLEX CORRECTION FILTER REAL 1X REAL 2X COMPLEX GAIN / PHASE OFFSET ADJUST OUTPUT DATA FORMATTER 8-18 BIT-WIDTH
IOUT<17:0> QOUT<17:0>
CLK TRIGIN IIN<17:0> QIN<17:0> CLKOUT ISTRB
TRIGOUT A<5:0> P<15:0> CS WR RD BUSY RESET
uP INTERFACE
INPUT MEMORY (2k x 32) FEEDBACK MEMORY (1k x 20) FBCLK FB<19:0>
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
Functional Block Diagram
ISL5239 Pre-Distortion Linearizer
IIN<17:0> QIN<17:0> CLKOUT
OFFSET BINARY
MUX
BYPASS
BYPASS
BYPASS PRE-D OR BYPASS PD I,Q INPUT OR TEST
BYPASS IF CONV.
BYPASS CORRECTION FILTER REAL 1X REAL 2X COMPLEX
BYPASS GAIN / PHASE OFFSET ADJUST. OUTPUT DATA FORMATTER 8-18 BIT-WIDTH
IOUT<17:0> QOUT<17:0>
DE-MUX ISTRB INPUT TYPE (PAR/SERIAL)
HALF HALF HALF BAND BAND BAND I / FILTER FILTER FILTER / / Q / / / 1 2 3 20 18 20 IFIP I,Q I CM TEST Q
TEST FUNC. SEL. OFFSET SCALE PD MAG. LUT DATA I LUT DATA Q LUT DELTA DATA I LUT DELTA DATA Q ACTIVE LUT LUT ADDR LUT ADDR AUTO INCR. PWR INTGR PER. PWR LOW PWR HIGH
LUT ADDRESS CALCULATION ADDR
BYPASS
MODE
HM, KM, LM, GM, DC OFFSETS OUTPUT WORD WIDTH SEL. OUTPUT VALUE TYPE COEF. DATA REAL PIPELINE SEL. COEF. ADDR. SERIAL INPUT EN. COEF. B SELECT
JTAG
POWER
2
DATA LUT
CHANNEL 3 MEMORY EFFECT COMPENSATION TMS TDI TCK TRST TDO
ISL5239
TRIGIN PD MAG. MAX MIN uP TRIG SEL IFIP I,Q PD I,Q PD MAG. INPUT SEL DATA
TRIGOUT
COEF. A COEF. B SERIAL TO PAR. POWER INTEGRATOR
THRESHOLD COMPARE
TRIG SER. OUTPUT EN. FB DELAY COUNT PAR. TO SERIAL
INPUT DELAY COUNT uP INPUT STATE FB STATE
SERIN SERCLK SERSYNC SEROUT
EXTERNAL MEMORY EFFECTS FPGA FBCLK FB<19:0>
uP FORMAT
ADDR
ADDR
DATA
INPUT CAPTURE MEMORY 2K CM TEST I,Q MEMORY SELECT
FEEDBACK CAPTURE MEMORY 1K
CLK A<5:0> P<15:0> CS WR RD BUSY RESET
uP INTERFACE
ISL5239 Pinout
196 CABGA
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A NC B ISTRB C A3 D CS E P0 F VCCIO G P7 H P10 J CLK K P13 L DCTEST M QIN16 N TRST P NC VCCC QIN12 QIN8 QIN5 QIN1 IOUT15 IOUT14 VCCIO GND IOUT6 IOUT5 VCCC NC NC QIN14 QIN10 VCCC QIN3 IOUT17 IIOUT12 IOUT10 IOUT8 GND VCCIO NC IOUT1 QIN15 QIN13 QIN11 QIN7 QIN4 IOUT16 GND IOUT7 VCCIO IOUT3 IOUT0 IOUT2 FBCLK TDI TMS QIN17 QIN9 QIN2 VCCIO IOUT13 IOUT9 VCCC IOUT4 FB1 TRIGIN FB2 TDO TCK BUSY QIN6 QIN0 VCCC GND IOUT11 GND FB0 VCCC FB3 FB4 GND RESET P14 P15 TRIGOUT FB7 FB6 FB5 FB8 P12 P6 P5 GND P11 SEROUT FB9 FB12 FB11 SERIN P1 P2 P3 P4 FB13 FB16 FB15 GND FB10 VCCC RD A4 WR IIN5 GND VCCC QOUT14 QOUT10 FB14 FB19 FB18 VCCC A1 A5 IIN13 IIN10 IIN6 IIN1 QOUT17 QOUT13 QOUT8 QOUT2 A0 A2 IIN15 IIN11 IIN8 IIN2 QOUT16 QOUT12 VCCC QOUT7 QOUT1 QOUT3 QOUT0 NC IIN17 IIN14 VCCC IIN7 IIN3 VCCIO VCCIO QOUT9 QOUT6 QOUT4 NC GND VCCC IIN16 IIN12 IIN9 IIN4 IIN0 QOUT15 GND QOUT11 GND VCCIO VCCC NC
VCCIO QOUT5
FB17
VCCIO
P8
P9
SERSYNC GND
VCCIO SERCLK CLKOUT
POWER PIN GROUND PIN
SIGNAL PIN THERMAL BALL NC (Do not connect)
Pin Descriptions
NAME POWER SUPPLY VCCC VCCIO GND Positive Device Core Power Supply Voltage, 1.8V 0.18V. Positive Device Input/Output Power Supply Voltage, 3.3V 0.165V. Common Ground, 0V TYPE DESCRIPTION
MICROPROCESSOR INTERFACE AND CONTROL CLK RESET P<15:0> I I I/O Input Clock. Rising edge drives all of the devices synchronous operations, except feedback capture. Reset. (Active Low). Asserting reset will clear all configuration registers to their default values, reset all internal states, and halt all processing. 16-bit bi-directional data bus that operates with A<5:0>, CS, RD, and WR to write to and read from the devices internal control registers. When the host system asserts CS and RD simultaneously, P<15:0> is an output bus, under all other conditions, it is an input bus. Bit 15 is the MSB.
3
ISL5239 Pin Descriptions (Continued)
NAME A<5:0> CS WR RD BUSY TYPE I I I I O DESCRIPTION 6-bit address bus that operates with P<15:0>, CS, RD, and WR to write to and read from the devices internal control registers. Bit 5 is the MSB. Chip Select. (active low). Enables device to respond to P access by enabling read or write operations. Write Strobe, (active low). The data on P<15:0> is written to the destination selected by A<5:0> on the rising edge of WR when CS is asserted (low). Read Strobe (Active Low). The data at the address selected by A(5:0) is placed on P<15:0> when RD is asserted (low) and CS is asserted (low). P Busy. (Active Low) Indicates that the P interface is busy. The device asserts BUSY during a read operation to indicate that the output data on P<15:0> is not ready, and it asserts this signal during a write operation to indicate that it is not available for another read or write operation yet.
EXTERNAL SERIAL INTERFACE SERCLK SERSYNC SEROUT SERIN O O O I Serial Clock. Clock signal provided to external device for serial input and output, derived from rising edge of CLK. Serial Sync. Active high single-cycle pulse that is time coincident with the first sample of the 32-bit serial data frame. Derived from by rising edge of CLK. Serial Output. Output data bit for the serial interface. Derived from the rising edge of CLK. Serial Input.Input data bit for serial interface. Derived from rising edge of CLK.
FEEDBACK INTERFACE FB<19:0> I Feedback Input Data. Parallel or serial data to be stored in the feedback memory. In parallel mode, all 20bits are stored on the rising edge of FBCLK. In serial mode, bit 0 is serial input data and bit 1 is serial sync, sampled at the rising edge of FBCLK. Input clock used for sampling the FB<19:0> pins.
FBCLK TRIGGER INTERFACE TRIGIN TRIGOUT DATA INPUT IIN<17:0> QIN<17:0> ISTRB CLKOUT DATA OUTPUT IOUT<17:0> QOUT<17:0> TEST ACCESS DCTEST
I
I O
Trigger input. Hardwired trigger source to be used to trigger an input/feedback capture. Sampled internally with rising edge of CLK. Trigger output. Indicated that the capture system has been triggered, either internally or externally.
I I I O
I input data. Real component of the complex input sample when input format is parallel. Alternating real and imaginary when input format is muxed. Selectable as 2's complement or offset binary. Q input data. Imaginary component of the complex input sample when input format is parallel. Unused in serial input format. I data strobe. (active high). Used in the muxed input format. When asserted, the input data buses contains valid I data. Input data clock. Output clock for the data source driving the IIN<17:0> and QIN<17:0> inputs. Input data busses sampled on the rising edge of CLK that generates the rising edge of CLKOUT.
I I
I output data. Real component of the complex output sample driven by the rising edge of CLK. Selectable as 2's complement or offset binary. Q output data. IMaginary component of the complex output sample driven by the rising edge of CLK. Selectable as 2's complement or offset binary.
O
DC tree output. NAND tree output for DC threshold test. Do not connect for normal operation.
JTAG TEST ACCESS PORT TMS TDI TCK TRST TDO I I I I O JTAG Test Mode Select. Internally pulled up. JTAG Test Data In. Internally pulled up. JTAG Test Clock. JTAG Test Reset (Active Low). Internally pulled-up. JTAG Test Data Out.
4
ISL5239 Functional Description
The ISL5239 is a full-featured digital pre-distortion part featuring a high-performance lookup-table based predistortion (PD) processing unit. It includes an interpolator for upsampling and supports all varieties of upconversion architectures with a programmable correction filter for equalization including both sin(x)/x correction and removal of frequency response imbalance between quadrature paths. It also features gain, phase, and offset compensation for direct upconversion, digital IF output for heterodyning, and input/output capture memories with internal/external triggering capabilities to facilitate closedloop feedback processing. System implementation is typically as shown in Figure 1. Although the power detect feedback is shown with one Analog to Digital Converter (ADC), coherently demodulated feedback signalsLO configurations with 1 or 2 ADC's are also supported. The block diagram on page 1 shows the internal functional units within the ISL5239. In the following sections each functional unit is described. The operation of the ISL5239 is controlled by the register map listed in Table 3. Detailed descriptions for each control/status register are given in Tables 4 through 48. The control/status registers are referred to in the discussion below. The clock divider generates the CLKOUT signal which is used to clock data from the input signal source. Typical input sources include the ISL5217 quad programmable upconverter, which is designed to operate seamlessly with the ISL5239. The interpolation factor is selectable in control word 0x02, bits 6:4 as x1, x2, x4, and x8. The x1 mode bypasses all three half-band filters. The x2 mode utilized HB1 and bypasses HB2 and HB3. The x4 mode utilized HB1 and HB2 and bypasses HB3. Finally, the x8 mode utilizes all three HBFs. Saturation status bits are provided for each of the three HBFs in the status register 0x03. Input data rates up to the CLK rate are supported, based on the requirement CLK >= Fs * IP, where Fs is the input rate of the incoming data and IP is the interpolation factor selected in control word 0x02.
BYPASS INPUT FORMATTER IIN<17:0> QIN<17:0> BYPASS BYPASS
HALF HALF HALF I BAND BAND BAND FILTER FILTER FILTER / / / /Q 1 2 3 20 20 20 18
FIGURE 2. INPUT FORMATTER AND INTERPOLATOR BLOCK DIAGRAM
Each half-band filter performs a x2 interpolation by inserting one zero between each input data sample, causing the sampling frequency to double. The resulting zero-stuffed data is then low pass filtered to reject the upsampling image. The half-band filter frequency responses are as shown in Figure 3.
HALFBAND FILTER 1 RESPONSE
FIGURE 1. SYSTEM OVERVIEW
0
-20
Input Formatter and Interpolator (IFIP)
The Input Formatter and Interpolator interfaces to the data source to provide for parallel data input via the IIN<17:0>, QIN<17:0> busses, or serial input via the IIN<17:0> input bus. In parallel input mode, both 18-bit input busses are used to allow for parallel I and Q sample loading. In serial mode, the data is input via the IIN<17:0> bus only, as the I sample followed by the Q sample with the ISTRB input asserted with each I sample. In this mode, the QIN<17:0> bus is not utilized. The input data format is selectable as either two's complement or offset binary. The Interpolator function is necessary because predistorting a signal results in a much wider bandwidth signal (typically 5x to 7x wider). The Input Formatter and Interpolator is depicted in Figure 2. Three interpolation rates (x2, x4, and x8) are supported by the cascade of three Half-Band (HB) Filters. The ISL5239 includes an on-chip clock divider to facilitate input clocking.
MAGNITUDE (dB)
-40 -60
-80
-100
-120
-140
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
NORMALIZED FREQUENCY (NYQUIST=1)
FIGURE 3. x2, HB1 ENABLED FREQUENCY RESPONSE
5
ISL5239
Pre-Distorter (PD)
HALFBAND FILTER 2 RESPONSE
0
-20
MAGNITUDE (dB)
-40
The function of the Pre-distorter is to compute the magnitude of the input signal, look up a complex distortion vector based on the magnitude, and apply that distortion to the input signal. The signal magnitude may be computed by any of three different methods: log of power, linear magnitude or linear power. The result is scaled and offset by programmable amounts and becomes the address into a Look-up Table (LUT). Two LUTs are available, one of which is `live' in the circuit and the other is offline and can be loaded via the processor interface. This configuration allows instantaneous switching of pre-distortion characteristics without unpredictable effects on the processed signal. The LUTs contain a complex distortion vector, as well as complex delta values which interact with an external Thermal/Memory calculation circuit to predict the effects of temperature changes on the RF amplifier's behavior and compensate. The average power into the amplifier is computed and transmitted serially off chip. The external circuits compute one or two memory effect coefficients which are combined with the complex delta values in the LUT to derive the final distortion vector. The distortion vector is a rectangular complex value which is multiplied with the input signal resulting in a magnitude based nonlinearity. Access to the LUT is optimized by the use of an auto incrementing address register which allows the tables to be updated with only one address register write operation. Control words 0x10 through 0x1d apply to the
-60
-80
-100
-120
-140
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
NORMALIZED FREQUENCY (NYQUIST=1)
FIGURE 3A. X4, HB1 AND HB2 ENABLED FREQUENCY RESPONSE
HALFBAND FILTER 3 RESPONSE
0
-20
MAGNITUDE (dB)
-40
-60
-80
-100
-120
-140
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
NORMALIZED FREQUENCY (NYQUIST=1)
FIGURE 3B. X8, HB1-HB3 ENABLED FREQUENCY RESPONSE
6
ISL5239
pre-distorter. The pre-distorter block diagram is shown in Figure 4.
FROM IFIP I Q I Q PRE-D OR BYPASS INPUT OR TEST
IF Converter (IFC)
The output of the pre-distorter is a complex baseband signal sampled at the system CLK rate. To provide greater system flexibility, the IF Converter function can change this in one of three different ways, providing frequency shifts, sample rate changes and complex to real conversions.
I Q
CM TEST
LUT ADDRESS CALCULATION
Real 1X
The real 1x operating mode shifts the signal up by Fs/4 and performs a complex to real conversion without changing the base sample rate. This mode has 1/2 the bandwidth of the original input signal, with the I output channel active and the Q output channel set to 0. The operation of the IF converter in this mode is shown in Figure 5.
BYPASS
TEST FUNC. SEL. OFFSET SCALE PD MAG. LUT DATA I LUT DATA Q LUT DELTA DATA I LUT DELTA DATA Q ACTIVE LUT LUT ADDR LUT ADDR AUTO INCR. COEF. B SELECT SERIAL INPUT EN. PWR INTGR PER. PWR LOW PWR HIGH
BYPASS
POWER
ADDR LUT DATA MEMORY EFFECT COMPENSATION
I Q FROM PD
HALF BAND FILTER ej(pi/2)(n)
I Re{*}
FIGURE 5. IF CONVERTER IN REAL 1X MODE OPERATION
POWER INTEGRATOR COEF. A COEF. B SERIAL TO PAR. SERIN
Real 2X
The real 2x operating mode converts complex to real at 2x the sample rate and shifts the signal up to Fs/2 (Fs/4 of the output rate). This mode has the same bandwidth as the original signal with the I channel carrying the first of twwo samples/clock and the Q channel carrying the second sample. The operation of the IF Converter in this mode is shown in Figure 6.
BYPASS I Q FROM PD 2 2 HALF BAND FILTER ej(pi/2)(n) Z-1 2 2 I Q
SER. OUTPUT EN.
PAR. TO SERIAL
SERCLK SERSYNC SEROUT
EXTERNAL MEMORY EFFECTS FPGA
FIGURE 4. PRE-DISTORTER BLOCK DIAGRAM
Serial Interface
The serial interface for the external memory effects calculation consists of outputs SERCLK, SERSYNC, and SEROUT and input SERIN. The serial output sends the 32bit unsigned average power off-chip for further processing. The data is transmitted via the SEROUT pin MSB first, with the first bit marked by a high pulse on the SERSYNC pin. The SERCLK rate is scaled such that 32 bits are transmitted in one period of the power integrator as controlled by register 0x18 bits 5:4. SEROUT is enabled by register 0x18 bit 12. The SERIN receives the thermal compensation parameters from external processing using the same SERCLK and SERSYNC used by the SEROUT. The chip expects to receive 32 bits of data sequentially on the SERIN pin: the MSB of A, followed by the rest of A, then the MSB of B, followed by the rest of B. The SERIN is enabled by register 0x18 bit 8. When SERIN is disabled, registers 0x19 and 0x1a supply the A and B parameters for the thermal compensation calculations. See Figure 16 for a detailed timing diagram of the serial interface.
Re{*}
FIGURE 6. IF CONVERTER IN REAL 2X MODE OPERATION
7
ISL5239
The IF converter frequency response is as shown in Figure 7, with the folding effect shown in Figure 7A for the x2, Fs/4 upconverter case.
IFC FILTER RESPONSE (x2 MODE)
0
Correction Filter (CF)
To compensate for imperfections in the analog filtering which takes place after D/A conversion, the correction filter provides an independent 13-tap FIR filter on each channel. These filters may be programmed to remove differential group delay and ripple characteristics of external analog circuits including sin(x)/x correction and frequency response imbalance between the I and Q channels using either amplitude or group delay. This allows for correction of the two physically separate I and Q analog response paths from the DAC's through the quadrature up-converter. It also provides correction of the bandpass response when operating in a complex frequency shifted IF mode. There are two possible correction filter modes.
-20
MAGNITUDE (dB)
-40
-60
-80
-100
-120
-140
Real 2X
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
NORMALIZED FREQUENCY (NYQUIST=1)
FIGURE 7. x2, IFC FREQUENCY RESPONSE
IFC FILTER RESPONSE (x2 MODE, WITH FOLDING)
0
When the IF Converter is set to generate 2x sampled real data, the Correction Filter must be reconfigured to process this data correctly. In this mode it effectively provides one 13tap block-mode filter when the coefficients for the two filters are programmed identically.
BYPASS
-20
I
2 2 Z-1 I/Q FIRs
MAGNITUDE (dB)
-40
-60
Q FROM IFC
Z-1 2
2
I Q
-80
FIGURE 9. CORRECTION FILTER IN REAL 2X MODE
-100
Complex or Real 1x
-120 -140 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
NORMALIZED FREQUENCY (NYQUIST=1)
When configured for operation in the complex mode, one 13tap filter is provided for each the I and Q channels. In Real 1x mode, the Q channel is not used.
BYPASS
FIGURE 7A. x2, IFC FREQUENCY RESP. WITH FOLDING
I Q FROM IFC I-CHAN FIR Q-CHAN FIR I Q
Complex
The complex operating mode simply shifts the complex baseband signal up by Fs/4 without any filtering or real conversion. The operation of the IF converter in this mode is shown in Figure 8.
BYPASS I Q FROM PD I Q ej(pi/2)(n)
FIGURE 10. CORRECTION FILTER IN COMPLEX MODE
Output Data Conditioner (ODC)
The Output Data Conditioner can apply I/Q balance corrections, DC offset corrections and output format conversions. To compensate for gain/phase imperfections in external analog modulation circuits which can result in poor image rejection and reduced dynamic range, the ODC provides an I/Q balance corrector. The I/Q balance corrector provides four coefficients to control the magnitude of the direct and
FIGURE 8. IF CONVERTER IN COMPLEX MODE OPERATION
8
ISL5239
cross-coupled term on both the I and Q channels. Typical implementation is as shown in Figure 10.
Feedback Memory
The feedback memory allows the user to capture data from an external system and to view the memory through the processor interface. The feedback memory is used to observe the signals coming out of the amplifier. The 1K deep memory grabs 20-bit data, either in parallel or serial format. The feedback capture memory has its own clock input, FBCLK, which must be synchronously derived from CLK and meet the timing requirements. Capture operations may be triggered by an external signal (TRIGIN), by magnitude threshold crossings detection programmed in the magnitude threshold maximum and minimum values, or by system software writing to the processor trigger bit in control word 0x04, bit 6. Separate programmable delays of up to 32k samples are provided for both input memory and feedback capture, allowing system delays to be calibrated out for optimum alignment prior to analysis. A TRIGOUT output is provided to indicates when a capture operation has begun. The processor interface to the capture memories is designed to minimize the time required for loading/unloading. Although access to the memories takes place through indirect address and data registers, auto incrementing of the address is supported so the address only needs to be written once to access the entire memory. The capture memory is as shown in Figure 13.
TRIGIN MAG COMP uP TRIG SEL IFC I,Q PD I,Q PD MAG INPUT SEL DATA TRIG INPUT DELAY COUNT FB DELAY COUNT uP INPUT STATE FB STATE ADDR uP FORMAT FBCLK FB<19:0>
FIGURE 11. IMBALANCE CORRECTION
The Output formatter also provides DC offset correction to 1/4 LSB for 18-bit outputs to reduce analog DC offsets introduced in external D/A conversion and modulation circuits which can degrade system performance by causing carrier feed through in complex baseband systems, or spurs at DC for IF systems. The ODC also provides programmable output precision 8 to 18-bits, with unbiased (convergent) rounding, since practical system designs will require D/A converters with fewer than 18-bits. Internal accuracy is in excess of 18-bits, and utilizes 20-bit data paths in critical areas. Additionally, both two's complement and offset binary formats are supported.
Capture Memory (CM)
The Capture Memory allows the capture and viewing of data from various points in the chip. The primary function is to capture the digital signals coming into the pre-distorter. The CM also provides a secondary mode, as it can provide stimulus directly to the pre-Distorter. The CM is comprised of both the Input and the Feedback Memories. The processor interface provides the access to view, input, and alter the memory data. Synchronized (triggered) capture of both input and feedback signals is a typical requirement of adaptive digital pre-distortion systems.
ADDR
DATA
INPUT CAPTURE MEMORY 2K CM TEST I,Q MEMORY SELECT
FEEDBACK CAPTURE MEMORY 1K
Input Memory
The input capture memory observes the signals going into the amplifier. The 2K deep memory grabs complex samples of data at one of three possible locations, either at the input to the pre-distorter, the output of the pre-distorter, or from its magnitude calculation. In addition to capturing input data, this memory may also be configured as a data source. The input capture memory may be pre-loaded with user defined data and `played' into the pre-distorter to stimulate the system with signals that will elicit a desired response.
uP INTERFACE
FIGURE 12. CAPTURE MEMORY BLOCK DIAGRAM
Memory Modes and Programming Instructions
Unless noted, the following discussion applies to both the input memory and feedback memory operations. Prior to invoking the memory to capture or send data, the control word 0x06, bits 14:0 input trigger delay counter, 0x08 bits 14:0 feedback trigger delay count, 0x05, bits 10:0 input length, 0x04, bits 2:1 input memory datain source or 0x04, bit 8 feedback input format, and 0x04, bits 5:4 trigger select registers must be loaded.
9
ISL5239
For the input data, the 0x04, bit 3 input data round bit must also be selected and the feedback memory length count is always set to 1024. To invoke memory operation, the 0x07, bit 4 feedback memory mode or bits 1:0 input memory mode and 0x04, bit 6 processor trigger must be controlled. There are three modes of operation -- capture, loop, and single-shot. The feedback memory does not have a loop mode. A synopsis of the three modes is described below.
Single/Capture Mode
The sequence for the single shot stimulus mode, input memory mode = SINGLE, and input memory capture mode = CAPTURE with input capture mode = DELAY are the identical. The function of the memory reading or writing provides the difference between the two modes. In the single shot case, the capture memories read data to the output bus, and in the capture mode, they write data to the memories. The sequence of operation in the Single/Capture mode is described below. The input capture status should be in IDLE and the input memory capture mode in DELAY with the input memory delay counter set to 0x0056. Note: The 15 LSBs of the input memory delay counter are valid for the delay count in this mode. After the trigger, Ox56 signifies there are 86 counts of delay before the start of the capture/send of data to/from the memory. The user invokes the capture mode by writing the input memory mode to CAPTURE. The system is in the capture mode and the input memory status is ARMED. The system waits for a trigger and the memory is idle at this point. When a trigger occurs, the trigger causes the delay counters to count 86 clocks of delay. At the end of the delay, the memories begin their writing sequence until input memory length data points are written. During the writing of data, the input memory status is LOADING. When the final input memory length point is written, the input memory status returns to IDLE and a new capture transaction can be initiated by writing CAPTURE to the input memory mode. For the Single Capture mode, the deviations from the sequence are the writing of the input memory mode to SINGLE, and the input memory status to SEND when reading of the data from memory. All other operations are analogous.
Capture Mode
There are two types of capture mode -- advanced trigger and single/capture. The advanced trigger mode allows data to be captured around a trigger point, and the quantity of the data captured after the trigger point is set by 0x06, bits 14:0. When input memory capture mode = DELAY, the delay register acts as a delay count prior to the capture or sending of data. The max delay in this case is 32768 counts or system clock ticks. The advanced trigger mode is used in capture mode only. With the feedback capture operations being analogous to the input memory, one feedback memory exception is its control register 0x08, bits 14:0. It has 10 LSBs of available capture space.
Advanced Trigger Capture Mode Sequence
The control register 0x0e, bit 13:12 input capture status, should be in IDLE. Set 0x06, bit 15, input memory capture mode to ADVANCE to signify an advanced trigger capture. 0x06, bits 14:0 set the input trigger delay counter to = 0x56 signifies there are 86 points captured after the occurrence of the trigger point, 0x0e, bit 10:0, input trigger position and all other points are captured prior to trigger point. Note: only the 11 lsbs are valid for the delay capture in this mode. The input trigger position is a read-only register and adding to it the 11 lsbs of the input trigger delay counter determines the position of the final data point captured after the trigger. If the input trigger position is 0x1ff, the final point captured occurred at address: 0x1ff + 0x56 = 0x255 or 597 (decimal). The user must set the input trigger delay counter prior to invoking the transaction of the capture. The user invokes the capture mode register by writing CAPTURE to 0x07, bit 1:0 input memory mode. The system is in the advanced trigger capture mode and 0x0e, bits 13:12, input capture status is ARMED. The system waits for a trigger as the memory is continuously being written into. When a trigger occurs, the trigger causes the memory to load the data till the memory address is equal to input trigger position + 11 lsbs of the input trigger delay counter. The memory address that is time coincident with the trigger occurrence latches to the input trigger position. During this period, the input capture status is LOADING. When the final capture point loads, the input capture status returns to IDLE and a new capture transaction can be initiated by writing CAPTURE to the input memory mode.
Loop Mode
This is a continuous play mode from the memories; therefore, the memories should contain valid data before invoking transactions. The length of each repeatable output stream is controlled by the input memory length. Upon outputting the final input memory length point, the hardware resets to play another set of input memory length points from the memory. The user invokes the loop mode by writing input memory mode to LOOP. The system is in the loop mode and the input memory status = SEND. The memory starts reading data continuously and a stop can be initiated by setting input memory mode to IDLE during the transaction. The input memory status returns to IDLE and a new loop transaction can be initiated by writing the input memory mode to LOOP. This is the only mode where immediate mode changes are acknowledged during its transaction cycle.
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ISL5239
General Comments About Modes
Once a trigger is detected in the ARMED condition, all following triggers are ignored during the sequence. The system does not acknowledge new triggers until a new transaction is invoked and re-armed. When a new mode is invoked, all subsequent invocations of new modes during the duration of its sequence is ignored, except in the loop mode. In the loop mode, an input memory mode change to IDLE is processed immediately. When in the IDLE, all controls, addresses, and data, default to the processor interface values. into the memory. The I data is read from the memory on the DataHigh register and the Q data, DataLow register. In the predistort magnitude input, the data is unsigned 16 bits and the software has to reshuffle the data to extract the original magnitude. The DataHigh contains only the predistorter magnitude bit 15, and the DataLow contains the pre-distorter magnitude 14:0.
Writing/Reading the Memories from the Processor Interface
In the auto-increment mode, the data is loaded in 16-bit increments. The low word is written or read first followed by the high word. The high word increments the address counter and generates the actual write to the memory. For reading, it just increments the counter. The input memory select 0x04, bit 12, selects the memory to be written to or read from. When writing or reading a specific address, the 0x0b address register must be loaded before the 0x0c and 0x0d memory data registers. In the write, the high word transaction will trigger the actual write to the memory and a low word must be written first. For additional details, see the uP interface section.
Triggers
When a capture memory is ARMED, i.e. waiting for a trigger to happen, the activation of the trigger occurs in three ways -- external, data dependent, and user invoked. The trigger select, 0x04, bits 5:4, provides the selection of the trigger source. When the pre-distorter magnitude bus values fall between the range of 0x09 minimum and 0x0a maximum, the data dependent trigger activates. The first of these transitions causes a trigger to be detected and the remaining triggers during the capture sequence is ignored. To invoke the user invoked trigger, 0x04, 5:4, set to processor, the programmer writes a TRIGGER to the 0x04, bit 6 processor trigger register. After a TRIGGER is in the field, the user initiates the trigger by just writing to that register. The user does not have to reset the trigger back to IDLE. By setting the processor trigger bit to IDLE when not in use, it keeps the circuit quiet and allows the user to write to other values at that address without causing a trigger to occur during operation. To disable the processor trigger, the user should change trigger select to something other than PROCESSOR and then change values in processor trigger. If trigger select is not set to PROCESSOR, the system ignores the trigger generated by processor trigger. The feedback and input memory circuit uses the same trigger; both circuits trigger at the same point with its operation registers causing different operations to occur. The user should monitor input memory status and feedback memory status simultaneously before activating triggers. Make sure both status registers are in ARMED before activating triggers or the results from the capture can be erroneous and data can be overwritten. Selecting processor trigger (register 0x04, bits 5:4 = 00) while arming the input and feedback memory circuits is a convenient way to ensure no unexpected triggers occur before confirming ARMED status of both circuits.
Microprocessor Interface
The microprocessor interface allows the ISL5239 to appear as a memory mapped peripheral to the P. All registers can be accessed through this interface. The interface consists of a 16 bit bidirectional data bus, P<15:0>, six bit address bus, A<5:0>, a write strobe (WR), a read strobe (RD) and a chip enable (CE). The interface is configured for separate read and write strobe inputs. The processor interface provides a simple parallel Data/Control/Address bus for monitoring and controlling its operation. The processor interface is asynchronous to the CLK, and BUSY signal is included to indicate when read and write operations are complete. The register configuration is master/slave, where the slave registers are updated from the masters and all reads access the slaves. The master registers are clocked by the P WR strobe, are writable and cleared by a hard reset. The slave registers are clocked by CLK, and are readable and cleared by either a hard or soft reset. The transfer of configuration data from the master register to the slave register occurs synchronously after an event and requires a four clock synchronization period. The P can perform back-to-back accesses to the register, but must maintain four fCLK periods between accesses to the same address. This limits the maximum P access rate for the RAM to 125MHz/4 = 31.25MHz.
Input Data to Input Memory
There are three sources of input data to the input memory -- interpolator, pre-distorter's data outputs, and the predistorter's magnitude. Data from the interpolator and the predistort output are the upper 16 bits with or without rounding. Only 16 of the original 20 bits of I or Q is loaded
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ISL5239
The address map and bit field details for the microprocessor interface is shown in the Tables 2-48. The procedures for reading and writing to this interface are provided below. 2. Perform a direct write to any/all control words 0x14, 0x15, or 0x16, in any order, by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. 3. Perform a direct write to control word 0x17 by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. The WR updates the contents of 0x014-0x017 and performs the auto increment, if enabled.
Microprocessor Read/Write Procedure
The ISL5239 offers the user microprocessor read/write access to all of the configuration registers and the capture memory.
Read Access to the LUT
Configuration Read/Write Procedure
Write Access to the Configuration Master Registers
Perform a direct write to the configuration master registers by setting up the address A<5:0>, data P<15:0>, enabling the CS input, and generating WR strobe. The rising edge of the WR initiates the transfer to the master register. Registers may be written in any order. 1. Write the global control register 0x00. 2. Write all remaining registers sequentially. 3. Load all IFIP, PD, IFC, CM and ODC coefficients and control words.
RD WR A<5:0> P<15:0> 0x00 xxxx 0x01 0x02 0x03 0x04 0x05
1. Perform a direct write to control word 0x13 by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. 0x13 selects the auto increment mode and the LUT address as specified in bit 9:0. 2. Perform a direct read of any/all control words 0x14, 0x15, 0x16, in any order, by dropping the RD line low to transfer data from the slave register selected by A<5:0> onto the data bus P<15:0>. 3. Perform a direct read of control word 0x17 by dropping the RD line low to transfer data from the slave register selected by A<5:0> onto the data bus P<15:0>. Reading from this control word performs the auto increment, if enabled.
Capture Memory Read/Write Procedure
Indirect addressing is used to access the Capture Memory. The control word 0x04, bit 12 selects whether the input or feedback memory is accessed and bit 13 selects the auto address increment or manual modes. Control word 0x0b is the memory address, and words 0x0c and 0x0d combine to form the 32-bit word which is written or read from the memory. The write to 0x0d triggers the write to the memory and the auto increment of the address, if enabled. When reading feedback capture memory, 0x0c bits 3:0 will contain the upper four bits, and 0x0d, bits 15:0 will be the remaining 15-bits.
FIGURE 13. CONFIGURATION WRITE TRANSFER
Read Access to the Configuration Slave Registers
1. Perform a direct read of a configuration register by dropping the RD line low to transfer data from the register selected by A<5:0> onto the data bus P<15:0>.
RD WR A<5:0> P<15:0> HI-Z DATA VALID 0X00 0X01 0X02 0X03 0X04 0X05
Write Access to the Capture Memory
1. Perform a direct write to control word 0x04 by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. 0x04 selects the auto increment mode and the input or feedback memories. 2. Perform a direct write to control word 0x0b by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. 0x0b selects the starting memory address. 3. Perform a direct write to 0x0c by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. 4. Perform a direct write to control word 0x0d by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. The WR updates the contents of 0x0c and 0x0d and performs the auto increment, if enabled.
FIGURE 14. CONFIGURATION READ TRANSFER
LUT Read/Write Procedure
Write Access to the LUT Memory
1. Perform a direct write to control word 0x13 by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. 0x13 selects the auto increment mode and the LUT address as specified in bit 9:0.
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ISL5239
Read Access to the Capture Memory
1. Perform a direct write to control word 0x04 by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. 0x04 selects the auto increment mode and the input or feedback memories. 2. Perform a direct read of 0x0c by dropping the RD line low to transfer data from the slave register selected by A<5:0> onto the data bus P<15:0>. 3. Perform a direct read of control word 0x0d by dropping the RD line low to transfer data from the slave register selected by A<5:0> onto the data bus P<15:0>. Reading from this control word performs the auto increment, if enabled.
Software Hard Reset
The P can issue a reset command through the global control register 0x00, bit 4. This reset is identical to asserting the RESET pin, except the control fields 0x00 and 0x01 are not affected, and the uP interface is not reset.
Software Soft Reset
The uP can issue a reset command through the global control register 0x00, bit 0, which is identical to a Software hard reset, but none of the control registers are reset. A soft reset leaves the device in an idle state.
JTAG Test
The IEEE 1149.1 Joint Test Action Group boundary scan standard operational codes shown in Table 9 are supported. A separate application note is available with implementation details and the BSDL file is available.
TABLE 1. JTAG OP CODES SUPPORTED INSTRUCTION EXTEST IDCODE SAMPLE/PRELOAD INTEST BYPASS OP CODE 0000 0001 0010 0011 1111
Correction Filter Read/Write Procedure
Write Access to the Correction Filter Coefficients
1. Perform a direct write to control word 0x28 by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. 0x28 selects the auto increment mode. 2. Perform a direct write to control word 0x29 by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. 0x29 selects the coefficient address for I or Q. 3. Perform a direct write to control word 0x2a by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. 4. Repeat step 3 until all 13 coefficients for I and for Q have been loaded as the master registers are transferred to the slaves when the last Q coefficient is written.
Power-up Sequencing
The ISL5239 core and I/O blocks are isolated by structures which may become forward biased if the supply voltages are not at specified levels. During the power-up and power-down operations, differences in the starting point and ramp rates of the two supplies may cause current to flow in the isolation structures which, when prolonged and excessive, can reduce the usable life of the device. In general, the most preferred case would be to power-up or down the core and I/O structures simultaneously. However, it is also safe to power-up the core prior to the I/O block if simultaneous application of the supplies is not possible. In this case, the I/O voltage should be applied within 10 ms to 100 ms nominally to preserve component reliability. Bringing the core and I/O supplies to their respective regulation levels in a maximum time frame of a 100 ms, moderates the stresses placed on both, the power supply and the ISL5239. When powering down, simultaneous removal is preferred, but It is also safe to remove the I/O supply prior to the core supply. If the core power is removed first, the I/O supply should also be removed within 10-100mS.
Read Access to the Correction Filter Coefficients
1. Perform a direct write to control word 0x028 by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. 0x28 selects the auto increment mode. 2. Perform a direct write to control word 0x029 by setting up the address on A<5:0>, data on P<15:0>, and generating a rising edge on WR. 3. Perform a direct read of 0x2a by dropping the RD line low to transfer data from the slave register selected by A<5:0> onto the data bus P<15:0>.
Latency
To be provided later.
Reset
There are three types of chip resets.
RESET pin
A hard reset can occur by asserting the input pin RESET which resets all chip registers to their default condition, and resets the uP interface.
Application Notes and Evaluation Boards
The ISL5239 operation can be demonstrated via the ISL5239EVAL1 board. All required hardware and Windows GUI software are supplied with both a user's manual and accompanying applications notes.
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ISL5239
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . +2.5VCCC, 4.6V VCCIO Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . GND -0.5V to 5.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (oC/W) 196 BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . 42 w/200 LFM Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . 38 w/400 LFM Air Flow . . . . . . . . . . . . . . . . . . . . . . . . . 36 Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 125oC For Recommended Soldering Conditions, See Tech Brief TB334.
Operating Conditions
Voltage Range Core, VCCC . . . . . . . . . . . . . . . . . . +1.71V to +1.89V Voltage Range I/O, VCCCIO (Note 3) . . . . . . . . . +3.135V to +3.465V Temperature Range Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to VCC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379. 2. With "direct attach" features (i.e., vias in the PCB), the thermal resistance is 36 without airflow, w/200 it is 33, w/400 it is 31oC/W. Tie 196 BGA package pins F6-9, G6-9, H6-9, J6-9 to heat sink or ground with vias to ensure maximum device heat dissipation. 3. Single supply operation of both the core VCCC and I/O VCCIO at 1.8V is not allowed.
DC Electrical Specifications VCCC = 1.8 5%, VCCIO = 3.3 5%, TA = -40oC to 85oC
PARAMETER Logical One Input Voltage Logical Zero Input Voltage Clock Input High Clock Input Low Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Input Pull-up Leakage Current Low Input Pull-up Leakage Current High Standby Power Supply Current Operating Power Supply Current SYMBOL VIH VIL VIHC VILC VOH VOL IL IH ISL ISH ICCSB ICCOP TEST CONDITIONS VCCC = 1.89V, VCCIO = 3.465V VCCC = 1.71V, VCCIO = 3.135V VCCC = 1.89V, VCCIO = 3.465V VCCC = 1.71V, VCCIO = 3.135V IOH = -2mA, VCCC = 1.71V, VCCIO = 3.135V IOL = 2mA, VCCC = 1.71V, VCCIO = 3.135V VIN = VCCIO or GND, VCCC = 1.89V, VCCIO = 3.465V VIN = VCCIO or GND, VCCC = 1.89V, VCCIO = 3.465V VIN = VCCIO or GND, VCCC = 1.89V, VCCIO = 3.465V, TMS, TRST, TDI VIN = VCCIO or GND, VCCC = 1.89V, VCCIO = 3.465V, TMS, TRST, TDI VCCC = 1.89V, VCCIO = 3.465V, Outputs Not Loaded f = 125MHz, VIN = VCCIO or GND, VCCIO = 3.465V, VCCC = 1.89V, Freq = 1MHz, VCCIO Open, All Measurements Are Referenced to Device Ground Freq = 1MHz, VCCIO Open, All Measurements are Referenced to Device Ground -10 -10 -100 MIN 2.0 2.0 2.6 VCC-0.2 0.2 1 1 -50 1 1 100 Typ MAX 0.8 0.8 0.4 10 10 10 3 500 300 100 5 5 UNITS V V V V V V A A A A mA(core) uA(I/O) mA (Core) mA(I/O), (Note 4) pF (Note 5) pF (Note 5)
Input Capacitance Output Capacitance NOTES:
CIN COUT
-
4. Power Supply current is proportional to operation frequency. Typical rating for ICCOP is 2.0 mA/MHz (core) and 0.5mA/MHz(I/O), 5. Capacitance TA = 25oC, controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes.
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ISL5239
AC Electrical Specifications
VCCC = 1.8 5%, VCCIO = 3.3 5%, TA = -40oC to 85oC (Note 6) SYMBOL f CLK t CLK t CH t CL t RS t RH t RPW t PSW t PHW t ASW t AHW t CSW t CHW t BDW t WSC t WHC t WPWH t WPWL t RSR t RHR t CSR t CHR t ASR t ASC t RE t RD t DR1 t DS t DH t CC01 t CC0N t PDC1 t CFBD t FS t FH t SD1 t SD2 t SC1 t SCN t DSS 2 (Note 7) -0.1 2 1 2 (Note 7) 2 (Note 7) 2 (Note 7) 2 (Note 7) 1 7 8 9 8 MIN 8.0 3 3 2 2 2 1 4 0 4 0 3 3 0 3 3 1 2 1 2 -2 3 2 2 MAX 125 8 8 6 7 7 8 8 tCLK - 2 UNITS MHz ns ns ns ns ns CLK Cycles ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLK Cycles ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
PARAMETER CLK Frequency CLK Period CLK High, FBCLK High CLK Low, FBCLK Low Setup Time RESET High to CLK (Note 8) Hold RESET High from CLK RESET Low Pulse Width (Note 7) Setup Time P<15:0> to WR Hold Time P<15:0> from WR Setup Time A<5:0> to WR Hold Time A<5:0> from WR Setup Time CS to WR Hold Time CS from WR Delay Time from WR to BUSY Setup Time WR to CLK (Note 9) Hold Time WR from CLK WR Pulse Width High WR Pulse Width Low Setup Time from RD to CLK Hold Time RD from CLK Setup Time from CS to CLK Hold Time CS from CLK Setup Time from A<5:0> to CS and RD (Note 7) Setup Time from A<5:0> to CLK Delay Time from CS and RD to P<15:0> Enable (Note 7) Delay Time from CS and RD to P<15:0> Disable (Note 7) Delay Time from CLK to P<15:0> valid Setup Time IIN<17:0>, QIN<17:0>, or ISTRB to CLK Hold Time IIN<17:0>, QIN<17:0>, or ISTRB from CLK Delay Time from CLK to CLKOUT in x1 Mode Delay Time from CLK to CLKOUT in x2, x4, x8 Mode Delay Time from CLK to IOUT<17:0>, QOUT<17:0> valid Time Skew from CLK to FBCLK (Note 7) Setup Time from FB<19:0> to FBCLK Hold Time FB<19:0> from FBCLK Delay Time from CLK to SERSYNC Delay Time from CLK to SEROUT Delay Time from CLK to SERCLK in Period_32 Mode Delay Time from CLK to SERCLK in Period_64 or Period_128 Modes Setup Time from SERIN to CLK (Note 7)
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ISL5239
AC Electrical Specifications
Hold Time SERIN from CLK (Note 7) Delay Time from CLK to TRIGOUT Setup Time from TRIGIN to CLK Hold Time TRIGIN from CLK Setup Time from TMS and TDI to TCK Hold Time TMS and TDI from TCK Delay Time from TCK to TDO valid Test Clock Frequency Output Rise/Fall Time (Note 7) NOTES: 6. AC tests performed with CL = 70pF. Input reference level for CLK is 1.5V, all other inputs 1.5V. Test VIH = 3.0V, VIHC = 3.0V, VIL = 0V, VOL = 1.5V, VOH = 1.5V. 7. Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes. 8. Can be asynchronous to CLK, specification guarantying which CLK edge the device comes out of reset on. 9. Can be asynchronous to CLK, specification guarantying which CLK edge the device begins the read cycle on. VCCC = 1.8 5%, VCCIO = 3.3 5%, TA = -40oC to 85oC (Note 6) (Continued) SYMBOL t DHS t PDC t DS1 t DH1 t TS t TH t TD fT t RF MIN 1 2 (Note 7) 2 2 3 3 8 50 3 7 MAX UNITS ns ns ns ns ns ns ns MHz ns
PARAMETER
AC Test Load Circuit
DUT S1
CL
SWITCH S1 OPEN FOR ICCSB AND ICCOP IOH 1.5V IOL
TEST HEAD CAPACITANCE
EQUIVALENT CIRCUIT
Waveforms
CLK tSC1,tSCN tCLK tCH tCL tCLK = 1 / FCLK SERCLK tSD1 SERSYNC tSD2 tRH tRPW RESET SERIN tRS SEROUT tDSS tDHS
CLK
FIGURE 15. CLOCK AND RESET TIMING
FIGURE 16. SERIAL INTERFACE RELATIVE TIMING
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ISL5239 Waveforms
CLK tDS tDH IN<17:0>, QIN<17:0>, ISTRB tCCO1, tCCON CLKOUT TRIGIN tPDC1 IOUT<19:0>, QOUT<19:0> VALID VALID VALID TRIGOUT tDS1 VALID VALID CLK tPDC tDH1
(Continued)
FIGURE 17. INPUT/OUTPUT TIMING
FIGURE 18. TRIGGER PORT TIMING
CLK
tCFBD
TCK tTS tTH
FBCLK tFS FB<19:0> TDO tFH TMS, TDI tTD
VALID
FIGURE 19. FEEDBACK TIMING
FIGURE 20. JTAG TIMING
CLK
CLK tRSR RD tWSC tWPWL tWHC tWPWH tBDW 4 CLK CYCLES tRHR
RD
WR
WR
BUSY tCSW tCHW CS tASW tAHW A<5:0> VALID tPSW tPHW P<15:0> VALID
BUSY tCSR CS tASC A<5:0> VALID tASR tRE P<15:0> VALID tDR1 tRD tCHR
FIGURE 21. MICROPROCESSOR WRITE TIMING
FIGURE 22. MICROPROCESSOR READ TIMING
17
ISL5239 Programming Information and Device Control Registers
TABLE 2. CONTROL REGISTER MAP ADDRESS (5:0) 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 20 21 28 29 2a 2b TYPE R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R Correction Filter IF Converter Pre-Distorter Capture Memory Input Formatter and Interpolator Global FUNCTION Chip Control Chip ID Control Status Control Length of Input Memory Loops Input Memory Capture Mode and Trigger Delay Operating Modes Feedback Memory Capture Mode and Trigger Delay Magnitude Threshold Minimum Value Magnitude Threshold Maximum Value Memory Address Memory Data LSW Memory Data MSW Input Memory Status Feedback Memory Status Control Magnitude Function Control Magnitude Function Scale Factor Look-Up Table Control Look-Up Table Delta Imaginary Data Look-Up Table Delta Real Data Look-Up Table Imaginary Data Look-Up Table Real Data Memory Effect Control Memory Effect Coefficient A Memory Effect Coefficient B Memory Effect Power Integrator LSW Memory Effect Power Integrator MSW Status Control Status Control Coefficient Index Coefficient Value Status DESCRIPTION RESET DEFAULT 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0002 0x0000 0x0000 0x0000 0x0000 0x0000
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ISL5239
TABLE 2. CONTROL REGISTER MAP (Continued) ADDRESS (5:0) 30 31 32 33 34 35 36 37 38 39 TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R FUNCTION Output Data Conditioner Control I-to-I (hm) Coefficient Q-to-I (km) Coefficient I-to-Q(Im) Coefficient Q-to-Q (gm) Coefficient I-Channel DC Offset MSW I-Channel DC Offset LSW Q-Channel DC Offset MSW Q-Channel DC Offset LSW Status TABLE 3. CHIP CONTROL TYPE: GLOBAL: ADDRESS: 0x00 BIT 15:11 10:8 FUNCTION Reserved ID Index Not Used Pointer that selects a pair of characters from the Chip Identification, where the Chip Identification is a string of 16 ASCII characters. The ChipID field provides access to the selected character pair. For example, if the Chip Identification is the first 16 letters of the alphabet,--"ABCD...P"--then setting ID_Index = PAIR_0, selects the left-most pair, AB, which can be accessed by reading the ChipID field. Setting ID_Index = PAIR_1, selects the pair, CD. 000 - Pair 0 001 - Pair 1 010 - Pair 2 011 - Pair 3 100 - Pair 4 101 - Pair 5 110 - Pair 6 111 - Pair 7 Not Used Control bit that resets the entire chip except the Processor Interface (PI) block. Identical to asserting RESET, except: (1) it does not reset the control fields, ID Index, Hard Reset, Soft Reset, and Chip ID. (2) it does not reset the PI Controller in the PI block. 0 - Reset not active (default). 1 - Reset is active for the entire chip except the PI block. Not Used. Control bit that is identical to Hard Reset except that it does not reset any control registers. 0 - Reset not active (default). 1 - Reset is active for the entire chip except the PI block and all control registers. TABLE 4. CHIP ID TYPE: GLOBAL: ADDRESS: 0x01 BIT 15:0 FUNCTION Chip ID DESCRIPTION Pair of ASCII character codes for the Chip Identification, where the Chip Identification is a string of 16 ASCII characters. The ChipID field provides access to the characters selected by ID_Index. From the example in the ID_Index description, reading ChipID with ID_Index = PAIR_0 returns the ASCII code for "AB". The ASCII code for "A" is 0x41, and the ASCII code for "B" is 0x42; therefore, ChipID would have the value 0x4142. DESCRIPTION DESCRIPTION RESET DEFAULT 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
7:5 4
Reserved Hard Reset
3:1 0
Reserved Soft Reset
19
ISL5239
TABLE 5. CONTROL TYPE: INPUT FORMATTER AND INTERPOLATOR, ADDRESS: 0x02 BIT 15 14 13:8 7 6:4 FUNCTION Reserved Clear Status Reserved Reserved Interpolation Factor Not used. Set high to clear all status bits, set low (default) to allow the status bits to update. Internal use only. Not used. The chip upsamples its input data by x1, x2, x4, or x8, and it performs the appropriate filtering to reject the images created by the upsampling operation. Interpolation by 1 bypasses all the interpolation filters. 000 - x1 (default) 001 - x2 011 - x4 111 - x8 010, 100, 101, 110 Internal Use Only. Not used. The type of sample sequence of the Input Formatter and Interpolator input data IIN<17:0>, QIN<17:0>. 0 - PARALLEL. (default) The chip receives I and Q data in parallel through IIN<17:0>, QIN<17:0>The chip ignores the input signal, ISTRB, in this mode. 1 - SERIAL. The chip receives I and Q data in a serial stream through IIN<17:0>. The serial stream alternates between I and Q samples, and the chip uses the input signal, ISTRB, to detect which samples are I and which samples are Q. The chip ignores the input signal QIN<17:0> in this mode. Allows selection of the input type as 2's complement or offset binary. 0 - 2's complement (default) Input data. 1 - Offset Binary Input data. Soft reset that, when high, resets all input formatter and interpolator circuitry except the control fields. TABLE 6. STATUS TYPE: INPUT FORMATTER AND INTERPOLATOR, ADDRESS: 0x03 BIT 15:14 13 12:8 7 6 5 4 3 2 1 0 FUNCTION Reserved Reserved Reserved HB 3 Q Saturation HB 3 I Saturation HB 2 Q Saturation HB 2 I Saturation HB 1Q Saturation HB 1I Saturation Serial Mode Error Serial Mode Error Active Not used. Internal use only. Internal use only. When high, bit indicates HB 3 saturated at least one sample in the Q channel since the last clear status command. Invalid when Interpolation factor < x8. When high, bit indicates HB 3 saturated at least one sample in the I channel since the last clear status command. Invalid when Interpolation factor < x8. When high, bit indicates HB 2 saturated at least one sample in the Q channel since the last clear status command. Invalid when Interpolation factor < x8. When high, bit indicates HB 2 saturated at least one sample in the I channel since the last clear status command. Invalid when Interpolation factor < x8. When high, bit indicates HB 1 saturated at least one sample in the Q channel since the last clear status command. Invalid when Interpolation factor < x2. When high, bit indicates HB 1 saturated at least one sample in the I channel since the last clear status command. Invalid when Interpolation factor < x2. When high, indicated the input formatter and interpolator block performed an illegal operation since the last clear status command. When high, indicates the input formatter and interpolator block is performing an illegal operation. Not impacted by the clear status command. DESCRIPTION DESCRIPTION
3 2
Reserved Input Sequence Type
1
Input Value Type
0
Soft Reset
20
ISL5239
TABLE 7. CONTROL TYPE: CAPTURE MEMORY, ADDRESS: 0x04 BIT 15:14 13 12 FUNCTION Reserved Address Auto Increment Memory Select Not used. When set high, automatically increments the memory address after any access operation (read or write). Selects the memory for access. 0 - Input memory (default). 1 - Feedback memory. Not used. Selects the feedback input format. 0 - Parallel (default) uses FB<19:0> as a 20-bit parallel input. 1 - Serial uses FB<0> as the input data bit and FB<1> as the serial sync, sampled at the rising edge of FBCLK. Not used. When high, enables the trigger. Low (default) is trigger disabled. Selects the trigger mode. 00 - Processor trigger used (default). 01 - Magnitude trigger when min threshold <= magnitude <= maximum threshold. 10 - External trigger. Not used. Select the input memory dataIn Source. 00 - Interpolator output (default). 01 - Pre-distortion Output. 10 - Pre-distortion Magnitude. When high, resets all the configuration memory circuitry except the control fields. Low is default. TABLE 8. LENGTH OF INPUT MEMORY LOOP TYPE: CAPTURE MEMORY, ADDRESS: 0x05 BIT 15:11 10:0 FUNCTION Reserved Input Length Not Used Length of the input memory loop. Specified from 20(1) to 211 (2047). Default = 0. Resets the input memory address to 0 when input length reached. Actual loop length is this value + 2. TABLE 9. INPUT MEMORY CAPTURE MODE AND TRIGGER DELAY TYPE: CAPTURE MEMORY, ADDRESS: 0x06 BIT 15 FUNCTION Input Memory Capture Mode DESCRIPTION Selects the active capture mode when the input capture memory is running. Identical to feedback capture mode except applies to the input memory. 0 - Delay. (default) Defines the beginning of the 2k sample capture window as the trigger point plus the input trigger delay counter samples. 1 - Advance. Defines the end of the 2k-sample capture window as the trigger point plus the input trigger delay counter samples. See control word 0x07, bit 1:0 for mode selection. Offset delay that defines the input memory capture window when control word 0x07, bits 1:0 = 01 (Capture mode). When control word 0x06, bit 15 is set to 0, delay mode, values selectable from 20 to 215 (0...32768). When control word 0x06, bit 15 is set to 1, advance mode, value selectable from 20 to 211 (0...2047). DESCRIPTION DESCRIPTION
11:9 8
Reserved Feedback Input Format
7 6 5:4
Reserved Processor Trigger Trigger Select
3 2:1
Reserved Input Memory Data in Source
0
CM Soft Reset
14:0
Input Trigger Delay Counter
21
ISL5239
TABLE 10. OPERATING MODES TYPE: CAPTURE MEMORY, ADDRESS: 0x07 BIT 15:5 4 FUNCTION Reserved Not used. DESCRIPTION
Feedback Memory Mode Selects the feedback memory operating mode as 0 - Idle. (default) Memory not operating. 1 - Capture. Memory is capturing data in accordance with the mode and trigger settings specified in control word 0x08. Reserved Input Memory Mode Not used. Selects the capture memory operating mode as 00 - Idle. (default) Memory not operating. 01 - Capture. Memory is capturing data in accordance with the mode and trigger settings specified in control word 0x06. 10 - Loop. Input memory plays back data in a continuous loop to provide stimulus. 11 - Single. Input memory plays back data in a one pass through its contents to provide stimulus.
3:2 1:0
TABLE 11. FEEDBACK MEMORY CATPURE MODE AND TRIGGER DELAY TYPE: CAPTURE MEMORY, ADDRESS: 0x08 BIT 15 FUNCTION Feedback Memory Capture Mode DESCRIPTION Selects the active capture mode when the feedback capture memory is running. Identical to input capture mode except applies to the feedback memory. 0 - Delay. (default) Defines the beginning of the 1k sample capture window as the trigger point plus the feedback trigger delay counter samples. 1 - Advance. Defines the end of the 1k-sample capture window as the trigger point plus the feedback trigger delay counter samples. See control word 0x07, bit 4 for mode selection Offset delay that defines the feedback memory capture window when control word 0x07, bits 4 = 1 (Capture mode) When control word 0x08, bit 15 is set to 0, delay mode, values selectable from 20 to 215 (0...32767) When control word 0x08, bit 15 is set to 1, advance mode, value selectable from 20 to 210 (0...1023) TABLE 12. MAGNITUDE THRESHOLD MINIMUM VALUE TYPE: CAPTURE MEMORY, ADDRESS: 0x09 BIT 15:0 FUNCTION Magnitude Threshold Minimum DESCRIPTION Default = 0. Value selectable from 20 to 216 (0...65535). Magnitude-based trigger is generated when the magnitude value is greater than or equal to this value and less than or equal to the value in control word 0x0a. TABLE 13. MAGNITUDE THRESHOLD MAXIMUM VALUE TYPE: CAPTURE MEMORY, ADDRESS: 0x0a BIT 15:0 FUNCTION Magnitude Threshold Maximum DESCRIPTION Default = 0. Value selectable from 20 to 216 (0...65535). Magnitude-based trigger is generated when the magnitude value is less than or equal to this value and greater than or equal to the value in control word 0x09 TABLE 14. MEMORY ADDRESS TYPE: CAPTURE MEMORY, ADDRESS: 0x0b BIT 15:11 10:0 FUNCTION Reserved Memory Address Not used. Index into memory value. Default = 0. Selectable from 20 to 211 (0...2047). DESCRIPTION
14:0
Feedback Trigger Delay Counter
22
ISL5239
TABLE 15. MEMORY DATA LSW TYPE: CAPTURE MEMORY, ADDRESS: 0x0c BIT 15:0 FUNCTION Memory Data <15:0> DESCRIPTION Lower 16 bits of capture memory data word. TABLE 16. MEMORY DATA MSW TYPE: CAPTURE MEMORY, ADDRESS: 0x0d BIT 15:0 FUNCTION Memory Data <31:16> DESCRIPTION Higher 16 bits of capture memory data word. Writing to this address triggers the write to the memory and increments the address counter when address auto increment, control word 0x04, bit 13 is set. Must write control word 0x0c first, to load the data values into memory. TABLE 17. INPUT MEMORY STATUS TYPE: CAPTURE MEMORY, ADDRESS: 0x0e BIT 15:14 13:12 FUNCTION Reserved Input Capture Status Not used. Read only register with status defined as: 00 - Idle, Memory access OK. 01 - Armed. Capture memory waiting for trigger. 10 - Loading. Capture memory in load mode. 11 - Send. Memory sends data to downstream modules. Read only register which records memory location of input trigger point. 20 to 211 (0...2047). TABLE 18. FEEDBACK MEMORY STATUS TYPE: CAPTURE MEMORY, ADDRESS: 0x0f BIT 15:14 13:12 FUNCTION Reserved Not used. DESCRIPTION DESCRIPTION
10:0
Input Trigger Position
Feedback Capture Status Read only register with status defined as: 00 - Idle, Memory access OK. 01 - Armed. Capture memory waiting for trigger. 10 - Loading. Capture memory in load mode. Reserved Feedback Trigger Position Not used. Read only register which records memory location of feedback trigger point. 20 to 210 (0...1023).
10 9:0
TABLE 19. CONTROL TYPE: PRE-DISTORTER, ADDRESS: 0x10 BIT 15:3 2 FUNCTION Reserved Test Not used. Selects use of test inputs 0 - Off. IIN<17:0>, QIN<17:0> in use for input stream. 1 - On. Use capture memory output for pre-Distorter input. Note: Test inputs are 16-bits wide and are MSB justified onto the pre-distorter 20-bit inputs by setting the four LSB's to zero. Disables processing and allows input data to flow to output without any pre-distorter modification. 0 - Pre-distorter is active and processing. 1 - Pre-distorter is bypassed. Software generated logic reset, which when high, resets the pre-distorter circuitry. Low is default. DESCRIPTION
1
Bypass
0
Reset
23
ISL5239
TABLE 20. MAGNITUDE FUNCTION CONTROL TYPE: PRE-DISTORTER, ADDRESS: 0x11 BIT 15:14 13:12 FUNCTION Reserved Magnitude Function Select Not used Selects the magnitude calculation function as: 00 - Log. Log base 2 of magnitude squared computed as log2(I2 + Q2) 01 - Linear. Linear magnitude computed as sqrt (I2 + Q2) 10 - Power. Magnitude squared computed as (I2 + Q2) Linear offset of magnitude function when calculating LUT address (e.g. power backoff) Selectable from (-1024...1024) in increments of 2-1. Note: Setting the LSB of this value permits rounding of the resulting address. Clearing the LSB causes truncation. (0xFFFFF --> 0x00000 maps to -1024 to 0, and 0x00001 -> 0x7FFFF maps to 0.5 to 1023.5). TABLE 21. I - MAGNITUDE FUNCTION SCALE FACTOR TYPE: PRE-DISTORTER, ADDRESS: 0x12 BIT 15:13 12:0 FUNCTION Reserved Address Scale Not Used. Linear scale of magnitude function when calculating LUT address (e.g. db/LSB) Selectable from (0.(64increment)), in increments of 2-7. TABLE 22. Q - LOOK-UP TABLE CONTROL TYPE: PRE-DISTORTER, ADDRESS: 0x13 BIT 15:14 13 FUNCTION Reserved Active LUT Not Used. Selects which ping pong LUT is currently in use. The opposite LUT shall be accessible through the processor interface. 0 - Use LUT 0, access LUT 1. 1 - Use LUT 1, access LUT 0. Set high to automatically increment LUT address after any access operation (read/write). Default is low, not auto increment. Not used. Address for index into LUT. Default = 0, pointer to next LUT location. TABLE 23. LOOK-UP TABLE DELTA IMAGINARY DATA TYPE: PRE-DISTORTER, ADDRESS: 0x14 BIT 15:14 13:0 FUNCTION Reserved LUT Data Delta Q Not used. Delta imaginary Data written to or read back from LUT. Delta Q controls memory effect. Selectable as (0.125...(0.125-increment)) in increments of 2-16. Default = 0. TABLE 24. LOOK-UP TABLE DELTA REAL DATA TYPE: PRE-DISTORTER, ADDRESS: 0x15 BIT 15:14 13:0 FUNCTION Reserved LUT Data Delta I Not used. Delta real data written to or read back from LUT. Delta I controls memory effect. Selectable as (0.125...(0.125-increment)) in increments of 2-16. Default = 0. TABLE 25. LOOK-UP TABLE IMAGINARY DATA TYPE: PRE-DISTORTER, ADDRESS: 0x16 BIT 15:0 FUNCTION LUT Data Q DESCRIPTION Imaginary distortion data written to or read back from LUT. Selectable as (-0.5...(0.5-increment)) in increments of 2-16. Default = 0. DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION
11:0
Address Offset
12 11:10 9:0
LUT Address Auto Increment Reserved LUT Address
24
ISL5239
TABLE 26. LOOK-UP TABLE REAL DATA TYPE: PRE-DISTORTER, ADDRESS 0x17 BIT 15:0 FUNCTION LUT Data I DESCRIPTION Real distortion data written to or read back from LUT. Selectable as (-0.5...(0.5-increment)) in increments of 2-16. Default = 0. TABLE 27. MEMORY EFFECT CONTROL TYPE: PRE-DISTORTER, ADDRESS: 0x18 BIT 15:13 12 11:9 8 7:6 5:4 FUNCTION Reserved Serial Output Enable Reserved Serial Input Enable Reserved Power Integrator Period Not used. Set to high to enable the external serial interface output pins. Default is low, disabled. Not used Set to high to enable the external serial interface input pin SERIN data to override the processor settings. Default is low, disabled, processor settings over-ride serial inputs. Not used. Select the number of samples in the power integrate/dump operation. Also controls the SERCLK frequency. 00 - 128 samples, SERCLK runs at CLK/4. 01 - 64 samples, SERCLK runs at CLK/2. 10 - 32 samples, SERCLK runs at CLK. Not used. Set to high to select A2, low to select B (default). TABLE 28. MEMORY EFFECT COEFFICIENT A TYPE: PRE-DISTORTER, ADDRESS: 0x19 BIT 15:0 FUNCTION Thermal Coef. A DESCRIPTION Coefficient A for memory effect selectable from (-1.0...(1-increment)) in increments of 2-15. If control word 0x18, bit 8 high, reading this control word returns the value from SERIN. TABLE 29. MEMORY EFFECT COEFFICIENT B TYPE: PRE-DISTORTER, ADDRESS: 0x1a BIT 15:0 FUNCTION Thermal Coef. B DESCRIPTION Coefficient B for memory effect selectable from (-1.0...(1-increment)) in increments of 2-15. If control word 0x18, bit 8 high, reading this control word returns the value from SERIN. TABLE 30. MEMORY EFFECT POWER INTEGRATOR LSW TYPE: PRE-DISTORTER, ADDRESS: 0x1b BIT 15:0 FUNCTION Power Integrator <15:0> Power integrator LSW. TABLE 31. MEMORY EFFECT POWER INTEGRATOR MSW TYPE: PRE-DISTORTER, ADDRESS: 0x1c BIT 15:0 FUNCTION DESCRIPTION DESCRIPTION DESCRIPTION
3:1 0
Reserved Thermal Coefficient B
Power Integrator <31:16> Power integrator MSW. The Power Integrator [31:0] forms an unsigned fixed point number with 9 integer and 23 fractional bits (u9.23).
25
ISL5239
TABLE 32. STATUS TYPE: PRE-DISTORTER, ADDRESS: 0x1d BIT 15:1 0 FUNCTION Reserved Reserved Not used. Internal use only. TABLE 33. CONTROL TYPE: IF CONVERTER, ADDRESS: 0x20 BIT 15:14 13:12 11:9 8 7:6 5:4 FUNCTION Reserved Reserved Reserved Reserved Reserved IF Conv. Mode Not used. Internal use only. Not used. Internal use only. Not used. Selects the operational mode of the IF converter as: 00 - Disabled. Default mode which zeroes data into pipeline. 01 - Real x1. Real I outputs only, shifted by Fs/4. 10 - Real x2. Real samples output shifted by Fs/4. The sample on the I port is the first, earlier, sample of the pair. 11 - Complex. Complex outputs shifted by Fs/4. Not used. When set high, clears the IF Conv. status bits. Set low for normal operation and to allow the status bits to update. When set high (default), bypasses the IF conv. stage. Set low for normal processing. When set high, resets the IF conv. state machine. Set low (default) for normal operation. TABLE 34. STATUS TYPE: IF CONVERTER, ADDRESS: 0x21 BIT 15:4 3:2 1 0 FUNCTION Reserved Reserved I Channel Saturation Q Channel Saturation Not used. Internal use only. When high, indicates the IF conv. saturated at least one sample since the last control word 0x20, bit 2 command. When high, indicates the IF conv. saturated at least one sample since the last control word 0x20, bit 2 command. TABLE 35. CONTROL TYPE: CORRECTION FILTER, ADDRESS: 0x28 BIT 15 14:12 11:10 9:8 7:5 4 3 2 1 0 FUNCTION Reserved Reserved Reserved Reserved Reserved Address Auto Increment Real Pipeline Select Clear Status Bypass Reserved Not used. Internal use only. Not used. Internal use only. Not used. Set high to automatically increment coef/address after any access operation (read/write). Low (default) is not auto increment. Set high to configure the filter to process muxed real data, with the values arriving on the IIN<17:0> port in serial fashion with I following Q. Set low (default) for complex operation. Set high to clear all status bits, low for normal status bit updates. Set high (default) to bypass the correction filter, low to enable processing. Not used. DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION
3 2 1 0
Reserved IF Conv. Status Clear IF Conv. Bypass IF Conv. Reset
26
ISL5239
TABLE 36. COEFFICIENT INDEX TYPE: CORRECTION FILTER, ADDRESS: 0x29 BIT 15:8 7:0 FUNCTION Reserved Coefficient Address Not used. Pointer to current LUT location. Default is 0. 0x00-0x7F are I coefficients, 0x80-0xff are Q coefficients. Master register to slave register transfer occurs after the processor interface last write to the Q coefficient. The circuit uses the slave registers. All reads are from the slave register values. There are 13 each I and Q coefficients. TABLE 37. COEFFICIENT VALUE TYPE: CORRECTION FILTER, ADDRESS: 0x2a BIT 15:0 FUNCTION Coefficient Data DESCRIPTION Coefficient data access. Default = 0, non centered coef. Default = 1 - 2(1-15) centered coef. TABLE 38. STATUS TYPE: CORRECTION FILTER, ADDRESS: 0x2b BIT 15:4 3:2 1 0 FUNCTION Reserved Reserved I Channel Saturation Q Channel Saturation Not used. Internal use only. When high indicates the correction filter saturated at least one sample since the last control word 0x28, bit 2 command. When high indicates the correction filter saturated at least one sample since the last control word 0x28, bit 2 command. TABLE 39. CONTROL TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x30 BIT 15:8 8 7:4 FUNCTION Reserved Reserved Output Word Width Not used. Internal use only. Select the width of the output data bus IOUT<17:0> and QOUT<17:0>. 0000 - 8 bits 0001 - 9 bits 0010 - 10 bits 0011 - 11 bits 0100 - 12 bits 0101 - 13 bits 0110 - 14 bits 0111 - 15 bits 1000 - 16 bits 1001 - 17 bits 1010 - 18 bits (default) Set high to select offset binary, low to select 2's compliment. Set high to clear all status bits, low to enable bits to be active. Set high (default) to bypass, low to enable output processing. Not used. DESCRIPTION DESCRIPTION DESCRIPTION
3 2 1 0
Output Format Status clear Bypass Reserved
27
ISL5239
TABLE 40. I-to-I (HM) COEFFICIENT TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x31 BIT 15:0 FUNCTION hm Coefficient DESCRIPTION I-to-I (hm) coefficient values loaded from the master registers to the slave registers when the user writes the last coefficient register in control word 0x38. The slave registers are used in the datapath. All reads return slave register values. Default 1-2(1-15). TABLE 41. Q-to-I (KM) COEFFICIENT TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x32 BIT 15:0 FUNCTION km Coefficient Q-to-I (km) master register. Default 0. TABLE 42. I-to-Q (LM) COEFFICIENT TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x33 BIT 15:0 FUNCTION lm Coefficient I-to-Q (lm) master register. Default 0. TABLE 43. Q-toQ (GM) COEFFICIENT TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x34 BIT 15:0 FUNCTION Gm Coefficient DESCRIPTION Q-to-Q (Gm) master register. Default 1-2(1-15) TABLE 44. I CHANNEL DC OFFSET MSW TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x35 BIT 15:4 3:0 FUNCTION Reserved DC I Offset <19:16> Not used. I DC offset master register containing the upper four bits of the I DC offset. TABLE 45. I CHANNEL DC OFFSET LSW TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x36 BIT 15:0 FUNCTION DC I Offset <15:0> DESCRIPTION I DC offset master register containing the lower 16 bits of the I DC offset. TABLE 46. Q CHANNEL DC OFFSET MSW TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x37 BIT 15:4 3:0 FUNCTION Reserved DC Q Offset <19:16> Not used. Q DC offset master register containing the upper four bits of the Q DC offset. TABLE 47. Q CHANNEL DC OFFSET LSW TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x38 BIT 15:0 FUNCTION DC Q Offset <15:0> DESCRIPTION Q DC offset master register containing the lower 16 bits of the Q DC offset. DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION
28
ISL5239
TABLE 48. STATUS TYPE: OUTPUT DATA CONDITIONER, ADDRESS: 0x39 BIT 15:4 3:2 1 0 FUNCTION Reserved Reserved I Channel Status Q Channel Status Not used. Internal use only. When high indicates that the output data conditioner saturated at least one sample since the last control word 0x30, bit 2 command. When high indicates that the output data conditioner saturated at least one sample since the last control word 0x30, bit 2 command. DESCRIPTION
29
ISL5239 Plastic Ball Grid Array Packages (BGA)
o
A1 CORNER A1 CORNER I.D.
A D
V196.15x15
196 BALL PLASTIC BALL GRID ARRAY PACKAGE INCHES SYMBOL A A1
E
MILLIMETERS MIN 0.31 0.93 0.41 14.90 12.90 MAX 1.50 0.41 1.11 0.51 15.10 13.10 196 1.0 BSC 14 x 14 0.10 0.12 NOTES 7 3 Rev. 1 12/00
MIN 0.012 0.037 0.016 0.587 0.508 196
MAX 0.059 0.016 0.044 0.020 0.595 0.516
A2 b D/E D1/E1
B
N e MD/ME
A1 CORNER
TOP VIEW 0.15 MCAB 0.006 0.08 MC 0.003 b
0.039 BSC 14 x 14 0.004 0.005
D1
bbb aaa
14 13 12 11 10 9 8 7 6 5 4 3 2 1
S
A
A1 A CORNER I.D. B C D E F G E1 H J K L M N P e S A BOTTOM VIEW ALL ROWS AND COLUMNS
NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 3. "MD" and "ME" are the maximum ball matrix size for the "D" and "E" dimensions, respectively. 4. "N" is the maximum number of balls for the specific array size. 5. Primary datum C and seating plane are defined by the spherical crowns of the contact balls. 6. Dimension "A" includes standoff height "A1", package body thickness and lid or cap height "A2". 7. Dimension "b" is measured at the maximum ball diameter, parallel to the primary datum C. 8. Pin "A1" is marked on the top and bottom sides adjacent to A1. 9. "S" is measured with respect to datum's A and B and defines the position of the solder balls nearest to package centerlines. When there is an even number of balls in the outer row the value is "S" = e/2.
A1 A2 bbb C C A SEATING PLANE SIDE VIEW aaa C
All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at website www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com 30


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